The present embodiments relate to digital-to-analog converters, and are more particularly directed to converters using resistor strings.
A digital-to-analog converter ("DAC") may be used in various types of electronic circuits, or itself may be formed in a single integrated circuit device. In operation, the DAC is used to convert an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal. For further background, a DAC illustrated as having a resistor string in a single dimension may be seen in co-pending U.S. patent application Ser. No. 09/342,878, entitled "Bit Interpolation In A Resistor String Digital-To-Analog Converter", filed Jun. 29, 1999, having the same inventors as the present application, and hereby incorporated herein by reference. However, the embodiments of this application pertain more favorably to a DAC having a meander resistor string and, thus, a description of a prior art system with such a string is described as further background immediately below.
FIG. 1 illustrates a typical configuration of a prior art DAC 10, and is detailed briefly here with additional understandings left to one skilled in the art. By way of example and as appreciated later, DAC 10 is a 4-input 16-output DAC, while numerous other dimensions may exist for different DAC configurations. In general and as detailed below, DAC 10 is operable to receive a 4-bit input word, designated from least significant bit to most significant bit as I0-I3, and in response to the magnitude of that input, to output a corresponding analog voltage. Before detailing this operation, it is first instructive to examine the devices and connections of DAC 10. In this regard, DAC 10 includes a series-connected resistor string designated generally at 12, and which forms a meander in that it serpentines back and forth. Additionally, DAC 10 is generally an array in nature, having a number of bit lines in the vertical dimension and a number word lines in the horizontal dimension. Since the example of DAC 10 presents a 4-input 16-output DAC, the array of DAC 10 includes four bit lines designated BL0 through BL3, and four word lines designated WL0 through WL3. Also for the current example of a 4-to-16 DAC, resistor string 12 includes fifteen resistive elements shown as R0 through R14. Resistive elements R0 through R14 may be formed using various techniques, where the particular technique is not critical to the present inventive teachings. Also in this regard, in an effort to maintain the linearity between the digital input and the analog output, a common concern in the art is to endeavor to ensure that each resistor in the string has as close to the same resistance value as all other resistors in the string. Moreover, a voltage source V.sub.REF1 is applied across resistor string 12, and may be of any suitable biasing voltage, which for current applications is typically on the order of 2 to 5 volts. In any event, given the equal resistance of each element in the string, the voltage division across the resistors is uniform.
Looking to the detailed connections with respect to the resistive elements in string 12, each resistive element provides two taps from which a voltage may be measured as detailed below. For example, looking to resistive element R0, it provides a tap T0 and a tap T1, while resistive element R1 shares the same tap T1 and provides another tap T2, and so forth. Each tap has a switching device connected between it and a corresponding output bit line. In the current example, each of these switching devices is an n-channel field effect transistor, and is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which the drain of the transistor is connected. For example, the drain of transistor ST0 is connected to tap T0, the drain of transistor ST1 is connected to tap T1, and so forth. Further, the switching transistors are arranged so that a like number of taps are coupled via corresponding switching transistors to a corresponding one of the bit lines. In the current example of DAC 10, four taps are coupled in this manner to a corresponding bit line. For example, taps T0 through T3 are coupled, via corresponding switching transistors ST0 through ST3, to bit line BL0. As another example, taps T4 through T7 are coupled, via corresponding switching transistors ST4 through ST7, to bit line BL1. Moreover, each bit line BL0 through BL3 is coupled via a respective column access transistor, CAT0 through CAT3, to a column decoder 14. More particularly and for reasons evident below, column decoder 14 is coupled to receive the two most significant bits (MSBs) of the 4-bit word input to DAC 10, and in response column decoder 14 controls the gates of column access transistors CAT0 through CAT3.
Returning now to switching transistors ST0 through ST15, and given the array nature of DAC 10, it is further appreciated that the switching transistors are arranged so that a like number of switching transistors are controlled, via connection to their gates, by a corresponding word line which is further connected to row decoder 16. In the current example of DAC 10, four switching transistors are coupled in this manner to a corresponding word line. For example, the gates of switching transistors ST0, ST7, ST8, and ST15, are coupled to word line WL0. As another example, the gates of switching transistors ST1, ST6, ST9, and ST14, are coupled to word line WL1. Lastly in this regard, and for reasons evident below, row decoder 16 is coupled to receive the two least significant bits (LSBs) of the 4-bit word input to DAC 10 (i.e., bits I1 and I0), and also the least significant bit ("lsb") of the 2 MSBs input to column decoder 14 (i.e., bit I2). In response to these bits, row decoder 16 controls the gates of switching transistors ST0 through ST15. More particularly, each least significant bit I0 and I1 is coupled as an input to a corresponding exclusive OR gate EOG0 and EOG1 as a first input, while the second input of exclusive OR gates EOG0 and EOG1 is connected to receive the least significant bit of the MSBs input to column decoder 14.
The operation of DAC 10 is now described, first in general and then more specifically through the use of a few examples. A 4-bit digital word is connected to inputs I0 through I3 and, ultimately causes signals to pass to column decoder 14 and row decoder 16. Generally, row decoder 16 includes sufficient logic circuitry or the like to respond by enabling one of word lines WL0 through WL3, thereby providing an enabling voltage to the gates of the four switching transistors coupled to the enabled word line. Similarly, column decoder 14 includes sufficient logic circuitry or the like to respond by enabling one of column access transistors CAT0 through CAT3, thereby causing the enabled transistor to pass the voltage from the corresponding one of bit lines BL0 through BL3 to output V.sub.OUT1. In a simple case, the result of the above operations may be viewed by correlating the value of the 4-bit input to one of the sixteen decimal tap numbers. For example, if the 4-bit digital word equals 0001 (i.e., decimal value 1), then through enabling a switching transistor and a column access transistor the voltage at tap T1 is coupled to V.sub.OUT1.
By way of detailed illustration of the operation of DAC 10, the example of an input equal to 0001 is now traced through DAC 10 in greater detail. From the input of 0001, its two MSBs are coupled to column decoder 14 and, thus, the value of 00 is received by column decoder 14. In response, column decoder 14 enables the gate of the column access transistor having a numeric identifier equal to the value of the MSBs. Here, the MSBs of 00 equal a decimal value of 0 and, thus, column decoder 14 enables the gate of column access transistor CAT0. Turning now to row decoder 16, it responds to the value of the two MSBs of the 4-bit input. However, note that these two MSBs pass through exclusive OR gates and, therefore, their values are unchanged when passed to row decoder 16 if the lsb equals 0, or their complements are passed to row decoder 16 if the lsb equals 1. Returning then to the example of a 4-bit input equal to 0001, the LSBs equal 01, and the lsb equals 0. Thus, the value of 01 is unchanged and reaches row decoder 16, and it enables the word line having a decimal numeric identifier equal to the value of the LSBs as received from gates EOG0 and EOG1. In the present example, therefore, row decoder 16 enables word line WL1 which, therefore, enables each of switching transistors ST1, ST6, ST9, and ST14. Recall also that column decoder 14 in this example enables column access transistor CAT0. As a result, the voltage from tap T1 passes via switching transistor ST1 to bit line BL0, and then passes via column access transistor CAT0 to V.sub.OUT1. Lastly, it is noted that the voltage at tap T1 is divided across one resistive element (i.e., R0) and, thus, for an input equal to 0001, the analog output voltage using voltage division is 1/15+L *V.sub.REF1.
To further illustrated in detail the operation of DAC 10, consider now the example of an input equal to 0111 as traced through DAC 10. At the outset, from the general operation described above, one skilled in the art will expect that since the decimal value of 0111 equals seven, then the tap selected by DAC 10 for output is tap T7. This expectation is now confirmed through a detailed examination of this example. From the input of 0111, its two MSBs of 01 are coupled to column decoder 14. In response, column decoder 14 enables the gate of the column access transistor having a decimal numeric identifier equal to the MSB values of 01 and, hence, the gate of column access transistor CAT1 is enabled. Turning now to row decoder 16, note first that the lsb of the MSBs in this example equals 1; consequently, gates EOG0 and EOG1 cause the complements of the LSBs to reach row decoder 16. Thus, the complements of the 11 LSBs are 00 and, therefore, the value of 00 reaches row decoder 16. In response, row decoder 16 enables word line WL0 since it has a numeric identifier equal to the value of the complemented LSBs. When word line WL0 is enabled, it enables each of switching transistors ST0, ST7, ST8, and ST15. Recall also that column decoder 14 in this example enables column access transistor CAT1. As a result, the voltage from tap T7 passes via switching transistor ST7 to bit line BL1, and then passes via column access transistor CAT1 to output V.sub.OUT1. Lastly, it is noted that the voltage at tap T7 is divided across seven of the fifteen resistive elements (i.e., R0 through R6) and, thus, for an input equal to 0111, the analog voltage output using voltage division is equal to 7/15+L *V.sub.REF1. Accordingly, the digital input of 0111 has been converted to an analog voltage which equals this divided voltage. Given this as well as the preceding example, one skilled in the art will further appreciate that with different digital inputs, any of the switching transistors of DAC 10 may be enabled followed by enabling one of the column access transistors, and for each such combination of transistors there is a corresponding output which represents a divided voltage between 0 volts or any value incrementing up from 0 volts by 1/15.sub.VREF1 and up to an output equal to V.sub.REF1.
The configuration of DAC 10 has been accepted in various contexts; however it also provides certain drawbacks. Particularly, the speed of the DAC may limited due to various circuit features. For example, the circuit includes various elements which impose capacitance and, hence, delay, on the time that is required for a tap voltage to charge the output. Specifically, such capacitance exists in the bit lines as well as in the access transistors. In addition, although not shown in FIG. 1, the output V.sub.OUT1 is typically connected to drive a sampling capacitor, where that capacitor provides an input to an amplifier for amplifying the DAC output. Naturally, this sampling capacitor also adds capacitance and consequential delay to the tap voltage. The delays arising from the above as well as from other aspects ascertainable by one skilled in the art may present difficulties, or may not be acceptable, in certain contexts. For example, some applications require DACs with rather large precision and operating at certain speeds. For example, digital audio applications require DACs with 16 bit precision and operating at a rate of at least 44 KHz. Thus, the preceding limitations may be critical given these or even greater circuit requirements. Still further, while increasing DAC speed is important, it is also often important for the DAC to be formed within a certain spatial area. In other words, while large bit precision and/or fast transition may be required, this often must be sought while also accommodating space constraints. Indeed, it is often the goal of an integrated circuit to be made smaller, and this goal may well apply to a DAC, either alone or in combination with other circuitry on the same single integrated circuit. With respect to the DAC, reducing its size is like to improve the linearity between the digital input and the analog output. In view of these drawbacks and goals, there arises a need to provide an improved DAC configuration, as is achieved by the preferred embodiments discussed below.